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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:21 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:21 -0700 |
commit | 997f36c7115e37f292c50db8986c6ebd4bd1beca (patch) | |
tree | 066f9abaa93c3dd1509d6f1b25acb731c64e87fa /src/arch/arm/regfile.hh | |
parent | aa031e1c116bc8bf22c844b4a9f3d2b3c69f995a (diff) | |
download | gem5-997f36c7115e37f292c50db8986c6ebd4bd1beca.tar.xz |
Registers: Collapse ARM and MIPS regfile directories.
--HG--
rename : src/arch/arm/regfile/misc_regfile.hh => src/arch/arm/misc_regfile.hh
rename : src/arch/arm/regfile/regfile.cc => src/arch/arm/regfile.cc
rename : src/arch/mips/regfile/misc_regfile.cc => src/arch/mips/misc_regfile.cc
rename : src/arch/mips/regfile/misc_regfile.hh => src/arch/mips/misc_regfile.hh
Diffstat (limited to 'src/arch/arm/regfile.hh')
-rw-r--r-- | src/arch/arm/regfile.hh | 72 |
1 files changed, 69 insertions, 3 deletions
diff --git a/src/arch/arm/regfile.hh b/src/arch/arm/regfile.hh index 91cc67be0..694351b0f 100644 --- a/src/arch/arm/regfile.hh +++ b/src/arch/arm/regfile.hh @@ -28,9 +28,75 @@ * Authors: Stephen Hines */ -#ifndef __ARCH_ARM_REGFILE_HH__ -#define __ARCH_ARM_REGFILE_HH__ +#ifndef __ARCH_ARM_REGFILE_REGFILE_HH__ +#define __ARCH_ARM_REGFILE_REGFILE_HH__ -#include "arch/arm/regfile/regfile.hh" +#include "arch/arm/types.hh" +#include "arch/arm/misc_regfile.hh" +#include "sim/faults.hh" + +class Checkpoint; +class EventManager; +class ThreadContext; + +namespace ArmISA +{ + enum FPControlRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR + }; + + enum FCSRBits { + Inexact = 1, + Underflow, + Overflow, + DivideByZero, + Invalid, + Unimplemented + }; + + enum FCSRFields { + Flag_Field = 1, + Enable_Field = 6, + Cause_Field = 11 + }; + + enum MiscIntRegNums { + zero_reg = NumIntArchRegs, + addr_reg, + + rhi, + rlo, + + r8_fiq, /* FIQ mode register bank */ + r9_fiq, + r10_fiq, + r11_fiq, + r12_fiq, + + r13_fiq, /* FIQ mode SP and LR */ + r14_fiq, + + r13_irq, /* IRQ mode SP and LR */ + r14_irq, + + r13_svc, /* SVC mode SP and LR */ + r14_svc, + + r13_undef, /* UNDEF mode SP and LR */ + r14_undef, + + r13_abt, /* ABT mode SP and LR */ + r14_abt + }; + + void copyRegs(ThreadContext *src, ThreadContext *dest); + + void copyMiscRegs(ThreadContext *src, ThreadContext *dest); + +} // namespace ArmISA #endif |