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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | 0cb180ea0dcece9157ad71b4136d557c2dbcf209 (patch) | |
tree | f65b3376cfe8cdad517f6a2a3a8c9e2cf69c987a /src/arch/arm/regfile/regfile.hh | |
parent | 25884a87733cd35ef6613aaef9a8a08194267552 (diff) | |
download | gem5-0cb180ea0dcece9157ad71b4136d557c2dbcf209.tar.xz |
Registers: Eliminate the ISA defined floating point register file.
Diffstat (limited to 'src/arch/arm/regfile/regfile.hh')
-rw-r--r-- | src/arch/arm/regfile/regfile.hh | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh index 6eefe5914..35830eabf 100644 --- a/src/arch/arm/regfile/regfile.hh +++ b/src/arch/arm/regfile/regfile.hh @@ -33,7 +33,6 @@ #include "arch/arm/types.hh" #include "arch/arm/regfile/int_regfile.hh" -#include "arch/arm/regfile/float_regfile.hh" #include "arch/arm/regfile/misc_regfile.hh" #include "sim/faults.hh" @@ -43,38 +42,39 @@ class ThreadContext; namespace ArmISA { + enum FPControlRegNums { + FIR = NumFloatArchRegs, + FCCR, + FEXR, + FENR, + FCSR + }; + + enum FCSRBits { + Inexact = 1, + Underflow, + Overflow, + DivideByZero, + Invalid, + Unimplemented + }; + + enum FCSRFields { + Flag_Field = 1, + Enable_Field = 6, + Cause_Field = 11 + }; + class RegFile { protected: IntRegFile intRegFile; // (signed) integer register file - FloatRegFile floatRegFile; // floating point register file public: void clear() { intRegFile.clear(); - floatRegFile.clear(); - } - - FloatReg readFloatReg(int floatReg) - { - return floatRegFile.readReg(floatReg); - } - - FloatRegBits readFloatRegBits(int floatReg) - { - return floatRegFile.readRegBits(floatReg); - } - - void setFloatReg(int floatReg, const FloatReg &val) - { - floatRegFile.setReg(floatReg, val); - } - - void setFloatRegBits(int floatReg, const FloatRegBits &val) - { - floatRegFile.setRegBits(floatReg, val); } IntReg readIntReg(int intReg) |