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author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
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committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
commit | 27b6148f47676c5c95022b3dcd606ceea4611818 (patch) | |
tree | 021d4e91a0a711335792ef5009a4e2246b4fb730 /src/arch/arm/regfile/regfile.hh | |
parent | a480ba00b96f4c2e872f5a01bfa1782500f1066e (diff) | |
download | gem5-27b6148f47676c5c95022b3dcd606ceea4611818.tar.xz |
ARM: Flush out the ARM's int_regfile.hh.
Diffstat (limited to 'src/arch/arm/regfile/regfile.hh')
-rw-r--r-- | src/arch/arm/regfile/regfile.hh | 30 |
1 files changed, 29 insertions, 1 deletions
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh index 05f9197c3..69d4252a6 100644 --- a/src/arch/arm/regfile/regfile.hh +++ b/src/arch/arm/regfile/regfile.hh @@ -32,7 +32,6 @@ #define __ARCH_ARM_REGFILE_REGFILE_HH__ #include "arch/arm/types.hh" -#include "arch/arm/regfile/int_regfile.hh" #include "arch/arm/regfile/misc_regfile.hh" #include "sim/faults.hh" @@ -65,6 +64,35 @@ namespace ArmISA Cause_Field = 11 }; + enum MiscIntRegNums { + zero_reg = NumIntArchRegs, + addr_reg, + + rhi, + rlo, + + r8_fiq, /* FIQ mode register bank */ + r9_fiq, + r10_fiq, + r11_fiq, + r12_fiq, + + r13_fiq, /* FIQ mode SP and LR */ + r14_fiq, + + r13_irq, /* IRQ mode SP and LR */ + r14_irq, + + r13_svc, /* SVC mode SP and LR */ + r14_svc, + + r13_undef, /* UNDEF mode SP and LR */ + r14_undef, + + r13_abt, /* ABT mode SP and LR */ + r14_abt + }; + class RegFile { public: |