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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-07-08 23:02:20 -0700 |
| commit | 3e2cad8370d99f45ecf4d922d3ac8213e0d72644 (patch) | |
| tree | 34a230e7364e94cb179cd07d1f8353a83dab4247 /src/arch/arm/regfile/regfile.hh | |
| parent | b8b7c7314ab6b7d9c7dc5315858274dc4c6b02ad (diff) | |
| download | gem5-3e2cad8370d99f45ecf4d922d3ac8213e0d72644.tar.xz | |
ARM: Use custom read/write code to alias R15 with the PC.
Diffstat (limited to 'src/arch/arm/regfile/regfile.hh')
| -rw-r--r-- | src/arch/arm/regfile/regfile.hh | 14 |
1 files changed, 2 insertions, 12 deletions
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh index 7f4d21353..5a812fecf 100644 --- a/src/arch/arm/regfile/regfile.hh +++ b/src/arch/arm/regfile/regfile.hh @@ -122,22 +122,12 @@ namespace ArmISA IntReg readIntReg(int intReg) { - // In the Arm, reading from the PC for a generic instruction yields - // the current PC + 8, due to previous pipeline implementations - if (intReg == PCReg) - return intRegFile.readReg(intReg) + 8; - //return pc + 8; - else - return intRegFile.readReg(intReg); + return intRegFile.readReg(intReg); } void setIntReg(int intReg, const IntReg &val) { - // Have to trap writes to PC so that they update NPC instead - if (intReg == PCReg) - setNextPC(val); - else - intRegFile.setReg(intReg, val); + intRegFile.setReg(intReg, val); } protected: |