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| author | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2009-06-21 09:21:07 -0700 |
| commit | 71e0d1ded278a85e33a628ddc842c975a216854f (patch) | |
| tree | 38b6d745885794a55021ab2f80f565dd4ed89fa8 /src/arch/arm/regfile | |
| parent | 19a1966079442ccbcda70c33bbcead7abb609985 (diff) | |
| download | gem5-71e0d1ded278a85e33a628ddc842c975a216854f.tar.xz | |
ARM: Pull some static code out of the isa desc and create miscregs.hh.
Diffstat (limited to 'src/arch/arm/regfile')
| -rw-r--r-- | src/arch/arm/regfile/misc_regfile.hh | 16 |
1 files changed, 0 insertions, 16 deletions
diff --git a/src/arch/arm/regfile/misc_regfile.hh b/src/arch/arm/regfile/misc_regfile.hh index f8301bed2..f7e5fbd98 100644 --- a/src/arch/arm/regfile/misc_regfile.hh +++ b/src/arch/arm/regfile/misc_regfile.hh @@ -43,22 +43,6 @@ namespace ArmISA return ""; } - //Coprocessor 0 Register Names - enum MiscRegTags { - // Status Registers for the ARM - // - // CPSR Layout - // 31302928 ... 7 6 5 4 3 2 1 0 - // N Z C V ... I F T { MODE } - CPSR = 0, - SPSR_FIQ, - SPSR_IRQ, - SPSR_SVC, - SPSR_UND, - SPSR_ABT, - FPSR - }; - class MiscRegFile { protected: |