Merge ARM into the head. ARM will compile but may not actually work.

2 files changed, 8 insertions, 5 deletions

diff --git a/src/arch/arm/regfile/regfile.cc b/src/arch/arm/regfile/regfile.cc
index 5de0b3076..a4d6e9a4a 100644
--- a/src/arch/arm/regfile/regfile.cc
+++ b/src/arch/arm/regfile/regfile.cc
@@ -55,7 +55,7 @@ MiscRegFile::copyMiscRegs(ThreadContext *tc)
 }
 
 void
-RegFile::serialize(std::ostream &os)
+RegFile::serialize(EventManager *em, ostream &os)
 {
     intRegFile.serialize(os);
     //SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
@@ -69,7 +69,7 @@ RegFile::serialize(std::ostream &os)
 }
 
 void
-RegFile::unserialize(Checkpoint *cp, const std::string &section)
+RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 {
     intRegFile.unserialize(cp, section);
     //UNSERIALIZE_ARRAY(floatRegFile);
diff --git a/src/arch/arm/regfile/regfile.hh b/src/arch/arm/regfile/regfile.hh
index 86799f18d..7f4d21353 100644
--- a/src/arch/arm/regfile/regfile.hh
+++ b/src/arch/arm/regfile/regfile.hh
@@ -38,11 +38,13 @@
 #include "sim/faults.hh"
 
 class Checkpoint;
+class EventManager;
 class ThreadContext;
 
 namespace ArmISA
 {
-    class RegFile {
+    class RegFile
+    {
       protected:
         IntRegFile intRegFile;		// (signed) integer register file
         FloatRegFile floatRegFile;	// floating point register file
@@ -176,8 +178,9 @@ namespace ArmISA
             //nnpc = val;
         }
 
-        void serialize(std::ostream &os);
-        void unserialize(Checkpoint *cp, const std::string &section);
+        void serialize(EventManager *em, std::ostream &os);
+        void unserialize(EventManager *em, Checkpoint *cp,
+                         const std::string &section);
 
         void changeContext(RegContextParam param, RegContextVal val)
         {