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| author | Gabe Black <gabeblack@google.com> | 2018-10-13 01:25:30 -0700 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-22 21:12:16 +0000 |
| commit | 774770a6410abb129e2a19de1ca50d7c0c311fef (patch) | |
| tree | 579e460775987782f64103e784527b2ae342eb14 /src/arch/arm/registers.hh | |
| parent | 2b80f588ab44c571c0355cd1b343fdd82f6f7b96 (diff) | |
| download | gem5-774770a6410abb129e2a19de1ca50d7c0c311fef.tar.xz | |
arm: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.
Change-Id: Ief1cd85d0eff7156282ddb1ce168a2a5677f7435
Reviewed-on: https://gem5-review.googlesource.com/c/13625
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/registers.hh')
| -rw-r--r-- | src/arch/arm/registers.hh | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 3e0a74e69..8346f454b 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -59,12 +59,6 @@ const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs + using ArmISAInst::MaxInstDestRegs; using ArmISAInst::MaxMiscDestRegs; -typedef RegVal IntReg; - -// floating point register file entry type -typedef RegVal FloatRegBits; -typedef FloatRegVal FloatReg; - // Number of VecElem per Vector Register, computed based on the vector length constexpr unsigned NumVecElemPerVecReg = 4; using VecElem = uint32_t; @@ -72,9 +66,6 @@ using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; using VecRegContainer = VecReg::Container; -// cop-0/cop-1 system control register -typedef RegVal MiscReg; - // condition code register; must be at least 32 bits for FpCondCodes typedef uint64_t CCReg; |