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author | Rekai Gonzalez-Alberquilla <Rekai.GonzalezAlberquilla@arm.com> | 2017-04-05 13:24:00 -0500 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-07-05 14:43:49 +0000 |
commit | 00da08902918da13fccc3f2266b7b2f5d0080708 (patch) | |
tree | b495a0ceba7e073adca005cf84a7575d0aad5f27 /src/arch/arm/registers.hh | |
parent | 0747a432d25ade2c197ca6393270e12606419872 (diff) | |
download | gem5-00da08902918da13fccc3f2266b7b2f5d0080708.tar.xz |
cpu: Added interface for vector reg file
This patch adds some more functionality to the cpu model and the arch to
interface with the vector register file.
This change consists mainly of augmenting ThreadContexts and ExecContexts
with calls to get/set full vectors, underlying microarchitectural elements
or lanes. Those are meant to interface with the vector register file. All
classes that implement this interface also get an appropriate implementation.
This requires implementing the vector register file for the different
models using the VecRegContainer class.
This change set also updates the Result abstraction to contemplate the
possibility of having a vector as result.
The changes also affect how the remote_gdb connection works.
There are some (nasty) side effects, such as the need to define dummy
numPhysVecRegs parameter values for architectures that do not implement
vector extensions.
Nathanael Premillieu's work with an increasing number of fixes and
improvements of mine.
Change-Id: Iee65f4e8b03abfe1e94e6940a51b68d0977fd5bb
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues and CC reg free list initialisation ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2705
Diffstat (limited to 'src/arch/arm/registers.hh')
-rw-r--r-- | src/arch/arm/registers.hh | 18 |
1 files changed, 15 insertions, 3 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 2e1ad1881..0a617e4dc 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011, 2014 ARM Limited + * Copyright (c) 2010-2011, 2014, 2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -43,10 +43,11 @@ #ifndef __ARCH_ARM_REGISTERS_HH__ #define __ARCH_ARM_REGISTERS_HH__ +#include "arch/arm/ccregs.hh" #include "arch/arm/generated/max_inst_regs.hh" #include "arch/arm/intregs.hh" -#include "arch/arm/ccregs.hh" #include "arch/arm/miscregs.hh" +#include "arch/generic/vec_reg.hh" namespace ArmISA { @@ -64,6 +65,13 @@ typedef uint64_t IntReg; typedef uint32_t FloatRegBits; typedef float FloatReg; +// Number of VecElem per Vector Register, computed based on the vector length +constexpr unsigned NumVecElemPerVecReg = 4; +using VecElem = uint32_t; +using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>; +using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>; +using VecRegContainer = VecReg::Container; + // cop-0/cop-1 system control register typedef uint64_t MiscReg; @@ -76,15 +84,19 @@ const int NumIntArchRegs = NUM_ARCH_INTREGS; const int NumFloatV7ArchRegs = 64; const int NumFloatV8ArchRegs = 128; const int NumFloatSpecialRegs = 32; +const int NumVecV7ArchRegs = 64; +const int NumVecV8ArchRegs = 32; +const int NumVecSpecialRegs = 8; const int NumIntRegs = NUM_INTREGS; const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; +const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; const int NumCCRegs = NUM_CCREGS; const int NumMiscRegs = NUM_MISCREGS; #define ISA_HAS_CC_REGS -const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; +const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs + NumMiscRegs; // semantically meaningful register indices const int ReturnValueReg = 0; |