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author | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
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committer | Yasuko Eckert <yasuko.eckert@amd.com> | 2013-10-15 14:22:44 -0400 |
commit | 2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2 (patch) | |
tree | 040fdd5bad814d7cb7ee40934974d2b38b28d67a /src/arch/arm/registers.hh | |
parent | 552622184752dc798bc81f9b0b395db68aee9511 (diff) | |
download | gem5-2c293823aa7cb6d2cac4c0ff35e2023ff132a8f2.tar.xz |
cpu: add a condition-code register class
Add a third register class for condition codes,
in parallel with the integer and FP classes.
No ISAs use the CC class at this point though.
Diffstat (limited to 'src/arch/arm/registers.hh')
-rw-r--r-- | src/arch/arm/registers.hh | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index cc4fac824..b9033fd5b 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -68,6 +68,9 @@ typedef float FloatReg; // cop-0/cop-1 system control register typedef uint64_t MiscReg; +// dummy typedef since we don't have CC regs +typedef uint8_t CCReg; + // Constants Related to the number of registers const int NumIntArchRegs = NUM_ARCH_INTREGS; // The number of single precision floating point registers @@ -76,6 +79,7 @@ const int NumFloatSpecialRegs = 8; const int NumIntRegs = NUM_INTREGS; const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; +const int NumCCRegs = 0; const int NumMiscRegs = NUM_MISCREGS; const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs; @@ -102,7 +106,8 @@ const int SyscallSuccessReg = ReturnValueReg; // These help enumerate all the registers for dependence tracking. const int FP_Reg_Base = NumIntRegs * (MODE_MAXMODE + 1); -const int Misc_Reg_Base = FP_Reg_Base + NumFloatRegs; +const int CC_Reg_Base = FP_Reg_Base + NumFloatRegs; +const int Misc_Reg_Base = CC_Reg_Base + NumCCRegs; // NumCCRegs == 0 const int Max_Reg_Index = Misc_Reg_Base + NumMiscRegs; typedef union { |