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| author | Gabor Dozsa <gabor.dozsa@arm.com> | 2019-06-11 11:47:26 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-07-18 15:09:22 +0000 |
| commit | 9130f5427d7009c4f40e0097b79b4972430a27c3 (patch) | |
| tree | 98f39295d24a16637c2fba641ef66b4a0741663a /src/arch/arm/registers.hh | |
| parent | ddd3f43f8a590cd287cd3449ea6e49bc48dad06a (diff) | |
| download | gem5-9130f5427d7009c4f40e0097b79b4972430a27c3.tar.xz | |
arch-arm: Add first-/non-faulting load instructions
First-/non-faulting loads are part of Arm SVE.
Change-Id: I93dfd6d1d74791653927e99098ddb651150a8ef7
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19177
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/registers.hh')
| -rw-r--r-- | src/arch/arm/registers.hh | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 8e6ce799b..3790d9d5c 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010-2011, 2014, 2016-2017 ARM Limited + * Copyright (c) 2010-2011, 2014, 2016-2018 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -89,8 +89,9 @@ const int NumIntRegs = NUM_INTREGS; const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs; const int VECREG_UREG0 = 32; -const int NumVecPredRegs = 17; // P0-P15, FFR +const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0 const int PREDREG_FFR = 16; +const int PREDREG_UREG0 = 17; const int NumCCRegs = NUM_CCREGS; const int NumMiscRegs = NUM_MISCREGS; |