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| author | Gabe Black <gabeblack@google.com> | 2018-11-21 16:20:57 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-02-01 01:22:19 +0000 |
| commit | a119a963240a35ab66a5baee3f77cfcd99c6bbbb (patch) | |
| tree | c883d37ed479e92c23d881a48b8f2abec469faf7 /src/arch/arm/registers.hh | |
| parent | fbdf0b689eb31543292f52c71d14152d8ff1156a (diff) | |
| download | gem5-a119a963240a35ab66a5baee3f77cfcd99c6bbbb.tar.xz | |
cpu, arch: Replace the CCReg type with RegVal.
Most architectures weren't using the CCReg type, and in x86 and arm
it was already a uint64_t.
Change-Id: I0b3d5e690e6b31db6f2627f449c89bde0f6750a6
Reviewed-on: https://gem5-review.googlesource.com/c/14515
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/arm/registers.hh')
| -rw-r--r-- | src/arch/arm/registers.hh | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh index 8960f9f92..fd59f3ed8 100644 --- a/src/arch/arm/registers.hh +++ b/src/arch/arm/registers.hh @@ -77,9 +77,6 @@ using VecPredRegContainer = ::DummyVecPredRegContainer; constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits; constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr; -// condition code register; must be at least 32 bits for FpCondCodes -typedef uint64_t CCReg; - // Constants Related to the number of registers const int NumIntArchRegs = NUM_ARCH_INTREGS; // The number of single precision floating point registers |