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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-04 16:27:04 +0100 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-04-27 16:00:28 +0000 |
| commit | 5187a24d496cd16bfe440f52ff0c45ab0e185306 (patch) | |
| tree | c491ebdad23a5f9e57ef62ffeabcf2b87289f5ce /src/arch/arm/stage2_mmu.cc | |
| parent | 685cf2d1f8ae2f2ca3168a650efa1d36120783fe (diff) | |
| download | gem5-5187a24d496cd16bfe440f52ff0c45ab0e185306.tar.xz | |
sim,cpu,mem,arch: Introduced MasterInfo data structure
With this patch a gem5 System will store more info about its Masters.
While it was previously keeping track of the Master name and Master ID
only, it is now adding a per-Master pointer to the SimObject related to
the Master.
This will make it possible for a client to query a System for a Master
using either the master's name or the master's pointer.
Change-Id: I8b97d328a65cd06f329e2cdd3679451c17d2b8f6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9781
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/arch/arm/stage2_mmu.cc')
| -rw-r--r-- | src/arch/arm/stage2_mmu.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc index 5c28d073e..ba820e339 100644 --- a/src/arch/arm/stage2_mmu.cc +++ b/src/arch/arm/stage2_mmu.cc @@ -51,7 +51,7 @@ using namespace ArmISA; Stage2MMU::Stage2MMU(const Params *p) : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb), port(_stage1Tlb->getTableWalker(), p->sys), - masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()->name())) + masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker())) { // we use the stage-one table walker as the parent of the port, // and to get our master id, this is done to keep things |