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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2018-06-04 09:40:19 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2018-06-11 16:55:30 +0000
commitf54020eb8155371725ab75b0fc5c419287eca084 (patch)
tree65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/arch/arm/stage2_mmu.cc
parent2113b21996d086dab32b9fd388efe3df241bfbd2 (diff)
downloadgem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers. Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/arch/arm/stage2_mmu.cc')
-rw-r--r--src/arch/arm/stage2_mmu.cc15
1 files changed, 8 insertions, 7 deletions
diff --git a/src/arch/arm/stage2_mmu.cc b/src/arch/arm/stage2_mmu.cc
index ba820e339..c6f3ba7c1 100644
--- a/src/arch/arm/stage2_mmu.cc
+++ b/src/arch/arm/stage2_mmu.cc
@@ -67,17 +67,17 @@ Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
Fault fault;
// translate to physical address using the second stage MMU
- Request req = Request();
- req.setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
+ auto req = std::make_shared<Request>();
+ req->setVirt(0, descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
if (isFunctional) {
- fault = stage2Tlb()->translateFunctional(&req, tc, BaseTLB::Read);
+ fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
} else {
- fault = stage2Tlb()->translateAtomic(&req, tc, BaseTLB::Read);
+ fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read);
}
// Now do the access.
- if (fault == NoFault && !req.getFlags().isSet(Request::NO_ACCESS)) {
- Packet pkt = Packet(&req, MemCmd::ReadReq);
+ if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
+ Packet pkt = Packet(req, MemCmd::ReadReq);
pkt.dataStatic(data);
if (isFunctional) {
port.sendFunctional(&pkt);
@@ -116,7 +116,8 @@ Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
}
void
-Stage2MMU::Stage2Translation::finish(const Fault &_fault, RequestPtr req,
+Stage2MMU::Stage2Translation::finish(const Fault &_fault,
+ const RequestPtr &req,
ThreadContext *tc, BaseTLB::Mode mode)
{
fault = _fault;