diff options
author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-04 09:40:19 +0100 |
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committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2018-06-11 16:55:30 +0000 |
commit | f54020eb8155371725ab75b0fc5c419287eca084 (patch) | |
tree | 65d379f7603e689e083e9a58ff4c2e90abd19fbf /src/arch/arm/stage2_mmu.hh | |
parent | 2113b21996d086dab32b9fd388efe3df241bfbd2 (diff) | |
download | gem5-f54020eb8155371725ab75b0fc5c419287eca084.tar.xz |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request*
to shared_ptr<Request>. Having memory requests being managed by smart
pointers will simplify the code; it will also prevent memory leakage and
dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10996
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Diffstat (limited to 'src/arch/arm/stage2_mmu.hh')
-rw-r--r-- | src/arch/arm/stage2_mmu.hh | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/arm/stage2_mmu.hh b/src/arch/arm/stage2_mmu.hh index b01b08153..8787089dc 100644 --- a/src/arch/arm/stage2_mmu.hh +++ b/src/arch/arm/stage2_mmu.hh @@ -70,12 +70,12 @@ class Stage2MMU : public SimObject class Stage2Translation : public BaseTLB::Translation { private: - uint8_t *data; - int numBytes; - Request req; - Event *event; - Stage2MMU &parent; - Addr oVAddr; + uint8_t *data; + int numBytes; + RequestPtr req; + Event *event; + Stage2MMU &parent; + Addr oVAddr; public: Fault fault; @@ -87,18 +87,18 @@ class Stage2MMU : public SimObject markDelayed() {} void - finish(const Fault &fault, RequestPtr req, ThreadContext *tc, + finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc, BaseTLB::Mode mode); void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId) { numBytes = size; - req.setVirt(0, vaddr, size, flags, masterId, 0); + req->setVirt(0, vaddr, size, flags, masterId, 0); } void translateTiming(ThreadContext *tc) { - parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read); + parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read); } }; |