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| author | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@arm.com> | 2013-01-07 13:05:35 -0500 |
| commit | 0d1ad50326a13a24daed916a069fc9f45775f51d (patch) | |
| tree | 69402307a753e23fb617538b93ad485f8e5b9598 /src/arch/arm/system.cc | |
| parent | 3db3f83a5ea4b9565db1ab6b22d18e2b33ecef98 (diff) | |
| download | gem5-0d1ad50326a13a24daed916a069fc9f45775f51d.tar.xz | |
arm: Make ID registers ISA parameters
This patch makes the values of ID_ISARx, MIDR, and FPSID configurable
as ISA parameter values. Additionally, setMiscReg now ignores writes
to all of the ID registers.
Note: This moves the MIDR parameter from ArmSystem to ArmISA for
consistency.
Diffstat (limited to 'src/arch/arm/system.cc')
| -rw-r--r-- | src/arch/arm/system.cc | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc index 380676bbb..b09784b64 100644 --- a/src/arch/arm/system.cc +++ b/src/arch/arm/system.cc @@ -105,11 +105,6 @@ ArmSystem::initState() // Set the initial PC to be at start of the kernel code threadContexts[0]->pcState(kernelEntry & loadAddrMask); } - - for (int i = 0; i < threadContexts.size(); i++) { - threadContexts[i]->setMiscReg(ArmISA::MISCREG_MIDR, - p->midr_regval); - } } ArmSystem::~ArmSystem() |