summaryrefslogtreecommitdiff
path: root/src/arch/arm/system.hh
diff options
context:
space:
mode:
authorAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:30 -0400
committerAndreas Hansson <andreas.hansson@arm.com>2015-05-05 03:22:30 -0400
commit23b9792681d4cd794b0ad74138160a37b8bdac8f (patch)
treedd849032f615ec6a5ff43a6a2e93393d8f6fd5f7 /src/arch/arm/system.hh
parent36f29496a019af4483430f17c4a6028b8dcfb2cf (diff)
downloadgem5-23b9792681d4cd794b0ad74138160a37b8bdac8f.tar.xz
arm: Remove unnecessary boot uncachability
With the recent patches addressing how we deal with uncacheable accesses there is no longer need for the work arounds put in place to enforce certain sections of memory to be uncacheable during boot.
Diffstat (limited to 'src/arch/arm/system.hh')
-rw-r--r--src/arch/arm/system.hh9
1 files changed, 0 insertions, 9 deletions
diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 599734fd3..0937f6376 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -133,15 +133,6 @@ class ArmSystem : public System
*/
virtual void initState();
- /** Check if an address should be uncacheable until all caches are enabled.
- * This exits because coherence on some addresses at boot is maintained via
- * sw coherence until the caches are enbaled. Since we don't support sw
- * coherence operations in gem5, this is a method that allows a system
- * type to designate certain addresses that should remain uncachebale
- * for a while.
- */
- virtual bool adderBootUncacheable(Addr a) { return false; }
-
virtual Addr fixFuncEventAddr(Addr addr)
{
// Remove the low bit that thumb symbols have set