ARM: Mark some variables uncacheable until boot all CPUs are enabled.

There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).

1 files changed, 9 insertions, 0 deletions

diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index 4898d433c..32b48a85b 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -78,6 +78,15 @@ class ArmSystem : public System
 
     void initState();
 
+    /** Check if an address should be uncacheable until all caches are enabled.
+     * This exits because coherence on some addresses at boot is maintained via
+     * sw coherence until the caches are enbaled. Since we don't support sw
+     * coherence operations in gem5, this is a method that allows a system
+     * type to designate certain addresses that should remain uncachebale
+     * for a while.
+     */
+    virtual bool adderBootUncacheable(Addr a) { return false; }
+
     virtual Addr fixFuncEventAddr(Addr addr)
     {
         // Remove the low bit that thumb symbols have set