arch-arm: adding register control flags enabling LSE implementation

Added changes on arch-arm architecture to accept Atomic instructions
following ARM v8.1 documentation. That includes enabling atomic bit
in ID registers and add have_lse variable into arm system.

Change-Id: Ic28d3215d74ff129142fb51cb2fa217d3b1482de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19809
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/src/arch/arm/system.hh b/src/arch/arm/system.hh
index e09f47706..46c58e8a1 100644
--- a/src/arch/arm/system.hh
+++ b/src/arch/arm/system.hh
@@ -130,6 +130,11 @@ class ArmSystem : public System
     /** SVE vector length at reset, in quadwords */
     const unsigned _sveVL;
 
+    /**
+     * True if LSE is implemented (ARMv8.1)
+     */
+    const bool _haveLSE;
+
     /** True if Priviledge Access Never is implemented */
     const unsigned _havePAN;
 
@@ -244,6 +249,9 @@ class ArmSystem : public System
     /** Returns the SVE vector length at reset, in quadwords */
     unsigned sveVL() const { return _sveVL; }
 
+    /** Returns true if LSE is implemented (ARMv8.1) */
+    bool haveLSE() const { return _haveLSE; }
+
     /** Returns true if Priviledge Access Never is implemented */
     bool havePAN() const { return _havePAN; }