diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-05-16 16:16:04 +0100 |
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committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2018-06-06 13:56:18 +0000 |
commit | 072f325b2b5686d2a5b19f17f808810d5afd1944 (patch) | |
tree | 374458b24bbb997408a834828b5a92bc848a30f4 /src/arch/arm/table_walker.cc | |
parent | 7f82aa3d60a1ca0f0b35435d42f875ff1f1bfe0b (diff) | |
download | gem5-072f325b2b5686d2a5b19f17f808810d5afd1944.tar.xz |
arch-arm: Respect EL from translation type
There are cases where instructions request translations in the context
of a lower EL. This is currently not respected in the TLB and the page
table walker. Fix that.
Change-Id: Icd59657a1ecfd8bd75a001bb1a4e41a6f4808a36
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10506
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Diffstat (limited to 'src/arch/arm/table_walker.cc')
-rw-r--r-- | src/arch/arm/table_walker.cc | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 26a07d70e..325a5128d 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -230,9 +230,15 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 // aarch32/translation/translation/AArch32.TranslateAddress dictates // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. - currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) || - ((currEL(_tc) == EL0) && ELIs64(_tc, EL1)); - currState->el = currEL(_tc); + if (isStage2) { + currState->el = EL1; + currState->aarch64 = ELIs64(_tc, EL2); + } else { + currState->el = + TLB::tranTypeEL(_tc->readMiscReg(MISCREG_CPSR), tranType); + currState->aarch64 = + ELIs64(_tc, currState->el == EL0 ? EL1 : currState->el); + } currState->transState = _trans; currState->req = _req; currState->fault = NoFault; @@ -363,17 +369,11 @@ TableWalker::processWalkWrapper() pendingChange(); currState = pendingQueue.front(); - ExceptionLevel target_el = EL0; - if (currState->aarch64) - target_el = currEL(currState->tc); - else - target_el = EL1; - // Check if a previous walk filled this request already // @TODO Should this always be the TLB or should we look in the stage2 TLB? TlbEntry* te = tlb->lookup(currState->vaddr, currState->asid, currState->vmid, currState->isHyp, currState->isSecure, true, false, - target_el); + currState->el); // Check if we still need to have a walk for this request. If the requesting // instruction has been squashed, or a previous walk has filled the TLB with @@ -439,7 +439,7 @@ TableWalker::processWalkWrapper() currState = pendingQueue.front(); te = tlb->lookup(currState->vaddr, currState->asid, currState->vmid, currState->isHyp, currState->isSecure, true, - false, target_el); + false, currState->el); } else { // Terminate the loop, nothing more to do currState = NULL; |