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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-08-02 10:38:01 +0100 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2016-08-02 10:38:01 +0100 |
| commit | 49538a71186d98f5440c5db646e23507fc2e38d1 (patch) | |
| tree | 96994897ff3faf3da05b44d2375afcc0b98140b9 /src/arch/arm/table_walker.cc | |
| parent | 4fbf40daab480ae02b75a75e0dd5f56ce38386d2 (diff) | |
| download | gem5-49538a71186d98f5440c5db646e23507fc2e38d1.tar.xz | |
arm: enable EL2 support
Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341
Diffstat (limited to 'src/arch/arm/table_walker.cc')
| -rw-r--r-- | src/arch/arm/table_walker.cc | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 91b13e251..1f0bdeb8e 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -1,5 +1,5 @@ /* - * Copyright (c) 2010, 2012-2015 ARM Limited + * Copyright (c) 2010, 2012-2016 ARM Limited * All rights reserved * * The license below extends only to copyright in the software and shall @@ -223,7 +223,7 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672 // aarch32/translation/translation/AArch32.TranslateAddress dictates // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64. - currState->aarch64 = opModeIs64(currOpMode(_tc)) || + currState->aarch64 = isStage2 || opModeIs64(currOpMode(_tc)) || ((currEL(_tc) == EL0) && ELIs64(_tc, EL1)); currState->el = currEL(_tc); currState->transState = _trans; @@ -255,12 +255,11 @@ TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint16_t _asid, currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL1); currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL1); break; - // @todo: uncomment this to enable Virtualization - // case EL2: - // assert(haveVirtualization); - // currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); - // currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); - // break; + case EL2: + assert(_haveVirtualization); + currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL2); + currState->tcr = currState->tc->readMiscReg(MISCREG_TCR_EL2); + break; case EL3: assert(haveSecurity); currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR_EL3); |