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author | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
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committer | Ali Saidi <Ali.Saidi@ARM.com> | 2010-11-15 14:04:03 -0600 |
commit | 4c2e5c282b334dcd263373c48d325c7f77847c61 (patch) | |
tree | 3139a60a9725b971ff26da6c0588f77a93bd0f0f /src/arch/arm/table_walker.cc | |
parent | 08c5673d56ddb77b3dd93d96b405c96c18c491d2 (diff) | |
download | gem5-4c2e5c282b334dcd263373c48d325c7f77847c61.tar.xz |
ARM: Add support for switching CPUs
Diffstat (limited to 'src/arch/arm/table_walker.cc')
-rw-r--r-- | src/arch/arm/table_walker.cc | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index c7c00924d..98dc1760d 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -43,6 +43,7 @@ #include "dev/io_device.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" +#include "sim/system.hh" using namespace ArmISA; @@ -59,9 +60,10 @@ TableWalker::~TableWalker() } -unsigned int TableWalker::drain(Event *de) +unsigned int +TableWalker::drain(Event *de) { - if (stateQueueL1.size() != 0 || stateQueueL2.size() != 0) + if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size()) { changeState(Draining); DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n"); @@ -75,6 +77,16 @@ unsigned int TableWalker::drain(Event *de) } } +void +TableWalker::resume() +{ + MemObject::resume(); + if ((params()->sys->getMemoryMode() == Enums::timing) && currState) { + delete currState; + currState = NULL; + } +} + Port* TableWalker::getPort(const std::string &if_name, int idx) { |