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| author | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-01 08:05:52 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2014-10-01 08:05:52 -0400 |
| commit | b520223699f51562140b8cc4a922eae64dffb3e3 (patch) | |
| tree | f5a82bf775b332f8817fb3b68502b41fdf663dd4 /src/arch/arm/table_walker.cc | |
| parent | 10f82934be924f265af4f10b15ca66106171f770 (diff) | |
| download | gem5-b520223699f51562140b8cc4a922eae64dffb3e3.tar.xz | |
arm: Use MiscRegIndex rather than int when flattening
Some additional type checking to avoid future issues.
Diffstat (limited to 'src/arch/arm/table_walker.cc')
| -rw-r--r-- | src/arch/arm/table_walker.cc | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc index 5f9d9b20d..91c7ab5d2 100644 --- a/src/arch/arm/table_walker.cc +++ b/src/arch/arm/table_walker.cc @@ -1158,9 +1158,10 @@ TableWalker::memAttrsLPAE(ThreadContext *tc, TlbEntry &te, // LPAE always uses remapping of memory attributes, irrespective of the // value of SCTLR.TRE - int reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; - reg = flattenMiscRegNsBanked(reg, currState->tc, !currState->isSecure); - uint32_t mair = currState->tc->readMiscReg(reg); + MiscRegIndex reg = attrIndx & 0x4 ? MISCREG_MAIR1 : MISCREG_MAIR0; + int reg_as_int = flattenMiscRegNsBanked(reg, currState->tc, + !currState->isSecure); + uint32_t mair = currState->tc->readMiscReg(reg_as_int); attr = (mair >> (8 * (attrIndx % 4))) & 0xff; uint8_t attr_7_4 = bits(attr, 7, 4); uint8_t attr_3_0 = bits(attr, 3, 0); |