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authorGiacomo Travaglini <giacomo.travaglini@arm.com>2019-05-01 15:21:03 +0100
committerGiacomo Travaglini <giacomo.travaglini@arm.com>2019-07-17 13:06:23 +0000
commit4dd475c1c0db6915f811a246c9e6fce8a61a6a77 (patch)
treeff494ce48de95600e3aac7cedc40905edcba2fdf /src/arch/arm/table_walker.cc
parentf9b549fbf572ac1b8b40ee86411eb9331a2bf458 (diff)
downloadgem5-4dd475c1c0db6915f811a246c9e6fce8a61a6a77.tar.xz
arch-arm: Use ExceptionLevel type in TlbEntry
Replacing uint8_t with ExceptionLevel type in the arm TlbEntry. The variable is representing the translation regime it is targeting. Change-Id: Ifcd6e86c5d73f752e8476a2b7fda9ea74a0c7a3b Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19488 Reviewed-by: Ciro Santilli <ciro.santilli@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/table_walker.cc')
-rw-r--r--src/arch/arm/table_walker.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index 461194d82..3feffa928 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -2064,7 +2064,7 @@ TableWalker::insertTableEntry(DescriptorBase &descriptor, bool longDescriptor)
if (currState->aarch64)
te.el = currState->el;
else
- te.el = 1;
+ te.el = EL1;
statPageSizes[pageSizeNtoStatBin(te.N)]++;
statRequestOrigin[COMPLETED][currState->isFetch]++;