ARM: Allow multiple outstanding TLB walks to queue.

1 files changed, 57 insertions, 37 deletions

diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index 8612df876..47fa9e376 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -48,6 +48,7 @@
 #include "params/ArmTableWalker.hh"
 #include "sim/faults.hh"
 #include "sim/eventq.hh"
+#include "base/fifo_buffer.hh"
 
 class DmaPort;
 class ThreadContext;
@@ -241,59 +242,77 @@ class TableWalker : public MemObject
 
     };
 
-    /** Port to issue translation requests from */
-    DmaPort *port;
+    struct WalkerState //: public SimObject
+    {
+        /** Thread context that we're doing the walk for */
+        ThreadContext *tc;
 
-    /** TLB that is initiating these table walks */
-    TLB *tlb;
+        /** Request that is currently being serviced */
+        RequestPtr req;
 
-    /** Thread context that we're doing the walk for */
-    ThreadContext *tc;
+        /** Context ID that we're servicing the request under */
+        uint8_t contextId;
 
-    /** Request that is currently being serviced */
-    RequestPtr req;
+        /** Translation state for delayed requests */
+        TLB::Translation *transState;
 
-    /** Context ID that we're servicing the request under */
-    uint8_t contextId;
+        /** The fault that we are going to return */
+        Fault fault;
 
-    /** Translation state for delayed requests */
-    TLB::Translation *transState;
+        /** The virtual address that is being translated */
+        Addr vaddr;
 
-    /** The fault that we are going to return */
-    Fault fault;
+        /** Cached copy of the sctlr as it existed when translation began */
+        SCTLR sctlr;
 
-    /** The virtual address that is being translated */
-    Addr vaddr;
+        /** Cached copy of the cpsr as it existed when the translation began */
+        CPSR cpsr;
 
-    /** Cached copy of the sctlr as it existed when translation began */
-    SCTLR sctlr;
+        /** Width of the base address held in TTRB0 */
+        uint32_t N;
+
+        /** If the access is a write */
+        bool isWrite;
+
+        /** If the access is not from user mode */
+        bool isPriv;
 
-    /** Cached copy of the cpsr as it existed when the translation began */
-    CPSR cpsr;
+        /** If the access is a fetch (for execution, and no-exec) must be checked?*/
+        bool isFetch;
 
-    /** Width of the base address held in TTRB0 */
-    uint32_t N;
+        /** If the mode is timing or atomic */
+        bool timing;
 
-    /** If the access is a write */
-    bool isWrite;
+        /** Save mode for use in delayed response */
+        BaseTLB::Mode mode;
 
-    /** If the access is not from user mode */
-    bool isPriv;
+        L1Descriptor l1Desc;
+        L2Descriptor l2Desc;
 
-    /** If the access is a fetch (for execution, and no-exec) must be checked?*/
-    bool isFetch;
+        /** Whether L1/L2 descriptor response is delayed in timing mode */
+        bool delayed;
 
-    /** If the mode is timing or atomic */
-    bool timing;
+        TableWalker *tableWalker;
 
-    L1Descriptor l1Desc;
-    L2Descriptor l2Desc;
+        void doL1Descriptor();
+        void doL2Descriptor();
+
+        std::string name() const {return tableWalker->name();}
+    };
 
-    /** Save mode for use in delayed response */
-    BaseTLB::Mode mode;
 
-    /** Whether L1/L2 descriptor response is delayed in timing mode */
-    bool delayed;
+    FifoBuffer<WalkerState> stateQueue;
+
+    /** Port to issue translation requests from */
+    DmaPort *port;
+
+    /** TLB that is initiating these table walks */
+    TLB *tlb;
+
+    /** Cached copy of the sctlr as it existed when translation began */
+    SCTLR sctlr;
+
+    WalkerState *currState;
 
   public:
     typedef ArmTableWalkerParams Params;
@@ -313,7 +332,8 @@ class TableWalker : public MemObject
             TLB::Translation *_trans, bool timing);
 
     void setTlb(TLB *_tlb) { tlb = _tlb; }
-    void memAttrs(ThreadContext *tc, TlbEntry &te, uint8_t texcb, bool s);
+    void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
+                  uint8_t texcb, bool s);
 
   private: