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authorAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
committerAnthony Gutierrez <atgutier@umich.edu>2012-08-15 10:38:08 -0400
commit0b3897fc90901953e9d016466c37ab507f85023c (patch)
tree0e8b1fec8d7c4871686903d573e9fd0fd8734d1e /src/arch/arm/table_walker.hh
parent5a648f2074caad8aee97e03f27e8eecc527a2cba (diff)
downloadgem5-0b3897fc90901953e9d016466c37ab507f85023c.tar.xz
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality for the O3 cpu and for the ARM ISA and adds some useful debug print statements. This is an incremental fix as there are still a few bugs/mem leaks with the switchout code. Particularly when switching from an O3CPU to a TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA I haven't encountered any more assertion failures; now the kernel will typically panic inside of simulation.
Diffstat (limited to 'src/arch/arm/table_walker.hh')
-rw-r--r--src/arch/arm/table_walker.hh5
1 files changed, 5 insertions, 0 deletions
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh
index db6b01cd4..1b95182c8 100644
--- a/src/arch/arm/table_walker.hh
+++ b/src/arch/arm/table_walker.hh
@@ -364,6 +364,9 @@ class TableWalker : public MemObject
/** Port to issue translation requests from */
SnoopingDmaPort port;
+ /** If we're draining keep the drain event around until we're drained */
+ Event *drainEvent;
+
/** TLB that is initiating these table walks */
TLB *tlb;
@@ -389,6 +392,8 @@ class TableWalker : public MemObject
return dynamic_cast<const Params *>(_params);
}
+ /** Checks if all state is cleared and if so, completes drain */
+ void completeDrain();
virtual unsigned int drain(Event *de);
virtual void resume();
virtual MasterPort& getMasterPort(const std::string &if_name,