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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-24 11:43:53 -0500 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-02-24 11:43:53 -0500 |
| commit | 1031b824b975cec999c37cabc8c05c485a4ae5ca (patch) | |
| tree | 18af5987accd59781642001849908ddb486d069a /src/arch/arm/table_walker.hh | |
| parent | 9f07d2ce7ecf435b9a1946f15fb3491bb4636637 (diff) | |
| download | gem5-1031b824b975cec999c37cabc8c05c485a4ae5ca.tar.xz | |
MEM: Move port creation to the memory object(s) construction
This patch moves all port creation from the getPort method to be
consistently done in the MemObject's constructor. This is possible
thanks to the Swig interface passing the length of the vector ports.
Previously there was a mix of: 1) creating the ports as members (at
object construction time) and using getPort for the name resolution,
or 2) dynamically creating the ports in the getPort call. This is now
uniform. Furthermore, objects that would not be complete without a
port have these ports as members rather than having pointers to
dynamically allocated ports.
This patch also enables an elaboration-time enumeration of all the
ports in the system which can be used to determine the masterId.
Diffstat (limited to 'src/arch/arm/table_walker.hh')
| -rw-r--r-- | src/arch/arm/table_walker.hh | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/table_walker.hh b/src/arch/arm/table_walker.hh index 520bfd9ac..22d2da5b3 100644 --- a/src/arch/arm/table_walker.hh +++ b/src/arch/arm/table_walker.hh @@ -44,6 +44,7 @@ #include "arch/arm/miscregs.hh" #include "arch/arm/tlb.hh" +#include "dev/io_device.hh" #include "mem/mem_object.hh" #include "mem/request.hh" #include "params/ArmTableWalker.hh" @@ -328,7 +329,7 @@ class TableWalker : public MemObject /** Port to issue translation requests from */ - DmaPort *port; + DmaPort port; /** TLB that is initiating these table walks */ TLB *tlb; |