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| author | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:49 -0500 |
|---|---|---|
| committer | Curtis Dunham <Curtis.Dunham@arm.com> | 2014-05-13 12:20:49 -0500 |
| commit | 5d029463eef3cfafa507dacadccd33402f82029a (patch) | |
| tree | d2549fad3b8d6e647b0f9cf9a06887346cb65902 /src/arch/arm/tlb.cc | |
| parent | e3b19cb294c98466a431950888045c6b5d24b675 (diff) | |
| download | gem5-5d029463eef3cfafa507dacadccd33402f82029a.tar.xz | |
cpu, mem: Make software prefetches non-blocking
Previously, they were treated so much like loads that they could stall
at the head of the ROB. Now they are always treated like L1 hits.
If they actually miss, a new request is created at the L1 and tracked
from the MSHRs there if necessary (i.e. if it didn't coalesce with
an existing outstanding load).
Diffstat (limited to 'src/arch/arm/tlb.cc')
0 files changed, 0 insertions, 0 deletions