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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:26 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2014-10-29 23:18:26 -0500 |
| commit | baf88e908d285191c13b5e96c16065957e5af7a6 (patch) | |
| tree | 7361d43b795f80a80a89995eb6865d51a972f36a /src/arch/arm/tlb.cc | |
| parent | 3a5c975fd7a0e6c8f25067c1794581056c01c22c (diff) | |
| download | gem5-baf88e908d285191c13b5e96c16065957e5af7a6.tar.xz | |
arm: Fix multi-system AArch64 boot w/caches.
Automatically extract cpu release address from DTB file.
Check SCTLR_EL1 to verify all caches are enabled.
Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index ef0702d44..46f124665 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -1089,7 +1089,14 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, req->setFlags(Request::UNCACHEABLE); } - req->setPaddr(te->pAddr(vaddr)); + Addr pa = te->pAddr(vaddr); + req->setPaddr(pa); + + if (!bootUncacheability && + ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(pa)) { + req->setFlags(Request::UNCACHEABLE); + } + if (isSecure && !te->ns) { req->setFlags(Request::SECURE); } |