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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | 1f032ad3452c2514287c142fb3faf953a5682ea3 (patch) | |
| tree | c37398638ecd1fcc43cb22c9c87f0384d7928127 /src/arch/arm/tlb.cc | |
| parent | 66bcbec96e9bb9619b306a281cb18e2b4cea91c5 (diff) | |
| download | gem5-1f032ad3452c2514287c142fb3faf953a5682ea3.tar.xz | |
ARM: Implement CLREX
Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 9cc00a89e..b7e951767 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -355,6 +355,13 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", cpsr.mode == MODE_USER, flags & UserMode); + // If this is a clrex instruction, provide a PA of 0 with no fault + // This will force the monitor to set the tracked address to 0 + // a bit of a hack but this effectively clrears this processors monitor + if (flags & Clrex){ + req->setPaddr(0); + return NoFault; + } if (!is_fetch) { assert(flags & MustBeOne); if (sctlr.a || !(flags & AllowUnaligned)) { |