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| author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
|---|---|---|
| committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
| commit | f29e09746a1380eb43d2309de37d56beec9afab7 (patch) | |
| tree | 1a9254adf1c75aa136753a05c92e83095875772e /src/arch/arm/tlb.cc | |
| parent | 4b9de4243943086294d7a2d7ab81a134d4fe5a49 (diff) | |
| download | gem5-f29e09746a1380eb43d2309de37d56beec9afab7.tar.xz | |
ARM: Fix Uncachable TLB requests and decoding of xn bit
Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index afa45901a..da2a34084 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -363,6 +363,10 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, req->setFlags(Request::UNCACHEABLE); return NoFault; } + if ((req->isInstFetch() && (!sctlr.i)) || + ((!req->isInstFetch()) && (!sctlr.c))){ + req->setFlags(Request::UNCACHEABLE); + } if (!is_fetch) { assert(flags & MustBeOne); if (sctlr.a || !(flags & AllowUnaligned)) { |