diff options
author | Andreas Sandberg <andreas.sandberg@arm.com> | 2016-02-16 13:21:04 -0600 |
---|---|---|
committer | Andreas Sandberg <andreas.sandberg@arm.com> | 2017-05-09 10:09:58 +0000 |
commit | f65c190d0b0185ca2965d09149f33cb78555a1bf (patch) | |
tree | b9d39c5fa71ee5002e257511c9a5731eaea7ab11 /src/arch/arm/tlb.cc | |
parent | 699773a867d1095790cce38744d9b2c38a1f551e (diff) | |
download | gem5-f65c190d0b0185ca2965d09149f33cb78555a1bf.tar.xz |
arm: Add support for memory-mapped m5ops
Add support for a memory mapped m5op interface. When enabled, the TLB
intercepts accesses in the 64KiB region designated by the
ArmTLB.m5ops_base parameter. An access to this range maps to a
specific m5op call. The upper 8 bits of the offset into the range
denote the m5op function to call and the lower 8 bits denote the
subfunction.
Change-Id: I55fd8ac1afef4c3cc423b973870c9fe600a843a2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2964
Diffstat (limited to 'src/arch/arm/tlb.cc')
-rw-r--r-- | src/arch/arm/tlb.cc | 27 |
1 files changed, 23 insertions, 4 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index eeccca0c0..6f7998db2 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -55,6 +55,7 @@ #include "arch/arm/system.hh" #include "arch/arm/table_walker.hh" #include "arch/arm/utility.hh" +#include "arch/generic/mmapped_ipr.hh" #include "base/inifile.hh" #include "base/str.hh" #include "base/trace.hh" @@ -81,12 +82,17 @@ TLB::TLB(const ArmTLBParams *p) isHyp(false), asid(0), vmid(0), dacr(0), miscRegValid(false), miscRegContext(0), curTranType(NormalTran) { + const ArmSystem *sys = dynamic_cast<const ArmSystem *>(p->sys); + tableWalker->setTlb(this); // Cache system-level properties haveLPAE = tableWalker->haveLPAE(); haveVirtualization = tableWalker->haveVirtualization(); haveLargeAsid64 = tableWalker->haveLargeAsid64(); + + if (sys) + m5opRange = sys->m5opRange(); } TLB::~TLB() @@ -129,6 +135,15 @@ TLB::translateFunctional(ThreadContext *tc, Addr va, Addr &pa) Fault TLB::finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const { + const Addr paddr = req->getPaddr(); + + if (m5opRange.contains(paddr)) { + req->setFlags(Request::MMAPPED_IPR | Request::GENERIC_IPR); + req->setPaddr(GenericISA::iprAddressPseudoInst( + (paddr >> 8) & 0xFF, + paddr & 0xFF)); + } + return NoFault; } @@ -582,7 +597,7 @@ TLB::translateSe(RequestPtr req, ThreadContext *tc, Mode mode, return std::make_shared<GenericPageTableFault>(vaddr_tainted); req->setPaddr(paddr); - return NoFault; + return finalizePhysical(req, tc, mode); } Fault @@ -1108,14 +1123,18 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, fault = testTranslation(req, mode, te->domain); } - // Generate Illegal Inst Set State fault if IL bit is set in CPSR if (fault == NoFault) { + // Generate Illegal Inst Set State fault if IL bit is set in CPSR if (aarch64 && is_fetch && cpsr.il == 1) { return std::make_shared<IllegalInstSetStateFault>(); } - } - return fault; + // Don't try to finalize a physical address unless the + // translation has completed (i.e., there is a table entry). + return te ? finalizePhysical(req, tc, mode) : NoFault; + } else { + return fault; + } } Fault |