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authorAli Saidi <Ali.Saidi@ARM.com>2009-11-17 18:02:08 -0600
committerAli Saidi <Ali.Saidi@ARM.com>2009-11-17 18:02:08 -0600
commit1470dae8e949eaef8232dc621d9074329357265c (patch)
tree687d5246ac61312f3201d8ddfe901fc0eb5a4118 /src/arch/arm/tlb.cc
parent171e7f7b24eead1fa82202549e3fad9a0df7b017 (diff)
downloadgem5-1470dae8e949eaef8232dc621d9074329357265c.tar.xz
ARM: Boilerplate full-system code.
--HG-- rename : src/arch/sparc/interrupts.hh => src/arch/arm/interrupts.hh rename : src/arch/sparc/kernel_stats.hh => src/arch/arm/kernel_stats.hh rename : src/arch/sparc/stacktrace.cc => src/arch/arm/stacktrace.cc rename : src/arch/sparc/system.cc => src/arch/arm/system.cc rename : src/arch/sparc/system.hh => src/arch/arm/system.hh rename : src/dev/sparc/T1000.py => src/dev/arm/Versatile.py rename : src/dev/sparc/t1000.cc => src/dev/arm/versatile.cc rename : src/dev/sparc/t1000.hh => src/dev/arm/versatile.hh
Diffstat (limited to 'src/arch/arm/tlb.cc')
-rw-r--r--src/arch/arm/tlb.cc10
1 files changed, 9 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index febc6d081..864c061a2 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -287,7 +287,15 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
return NoFault;
#else
- fatal("translate atomic not yet implemented\n");
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
+ if (!sctlr.m) {
+ req->setPaddr(req->getVaddr());
+ return NoFault;
+ }
+ panic("MMU translation not implemented\n");
+ return NoFault;
+
+
#endif
}