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authorGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
committerGabe Black <gblack@eecs.umich.edu>2010-06-02 12:58:10 -0500
commit1d5233958ad208e3b229e394ba5ab689b82d8cac (patch)
treede69dd4bac297c10f9e6355b06b5e1f5f12c9e90 /src/arch/arm/tlb.cc
parent7b397925af7fd9864189387179137dd4ac40dfad (diff)
downloadgem5-1d5233958ad208e3b229e394ba5ab689b82d8cac.tar.xz
ARM: Implement the V7 version of alignment checking.
Diffstat (limited to 'src/arch/arm/tlb.cc')
-rw-r--r--src/arch/arm/tlb.cc13
1 files changed, 12 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index 5ed77aea1..94f4019d6 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -291,6 +291,18 @@ Fault
TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
{
Addr vaddr = req->getVaddr() & ~PcModeMask;
+ SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
+ uint32_t flags = req->getFlags();
+
+ if (mode != Execute) {
+ assert(flags & MustBeOne);
+
+ if (sctlr.a || (flags & AllowUnaligned) == 0) {
+ if ((vaddr & flags & AlignmentMask) != 0) {
+ return new DataAbort;
+ }
+ }
+ }
#if !FULL_SYSTEM
Process * p = tc->getProcessPtr();
@@ -301,7 +313,6 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode)
return NoFault;
#else
- SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
if (!sctlr.m) {
req->setPaddr(vaddr);
return NoFault;