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| author | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:27 -0500 |
|---|---|---|
| committer | Ali Saidi <Ali.Saidi@ARM.com> | 2011-04-04 11:42:27 -0500 |
| commit | 55920a5ca73ded58762f1b7ae25c8cfe8c9e407d (patch) | |
| tree | b0bd2754e8b06b0080d0b9d22dbf4c721b209622 /src/arch/arm/tlb.cc | |
| parent | 5962fecc1d2eaf956f0aab10eee1e0666a461706 (diff) | |
| download | gem5-55920a5ca73ded58762f1b7ae25c8cfe8c9e407d.tar.xz | |
ARM: Fix table walk going on while ASID changes error
Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index f1c8ae41a..ccbca3d9c 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -446,8 +446,10 @@ Fault TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing) { - if (!miscRegValid) + if (!miscRegValid) { updateMiscReg(tc); + DPRINTF(TLBVerbose, "TLB variables changed!\n"); + } Addr vaddr = req->getVaddr(); uint32_t flags = req->getFlags(); @@ -456,7 +458,7 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, bool is_write = (mode == Write); bool is_priv = isPriv && !(flags & UserMode); - DPRINTF(TLBVerbose, "CPSR is user:%d UserMode:%d\n", + DPRINTF(TLBVerbose, "CPSR is priv:%d UserMode:%d\n", isPriv, flags & UserMode); // If this is a clrex instruction, provide a PA of 0 with no fault // This will force the monitor to set the tracked address to 0 |