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authorAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:08 -0500
committerAli Saidi <Ali.Saidi@ARM.com>2011-08-19 15:08:08 -0500
commitc9d5985b8221459e4737c637910dc08513b05660 (patch)
treedabd7d25ff8615d9c3dbac5de05c23e0a6e9eca2 /src/arch/arm/tlb.cc
parentc9c2d979b8c505d0013beb4b4b3e1885963e8d39 (diff)
downloadgem5-c9d5985b8221459e4737c637910dc08513b05660.tar.xz
ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via cache maintence instructions until all processors enable their MMUs & TLBs. Writes to these locations are manually flushed from the cache to main memory when the occur so that cores operating without their MMU enabled and only issuing uncached accesses can receive the correct data. Unfortuantely, gem5 doesn't support any kind of software directed maintence of the cache. Until such time as that support exists this patch marks the specific cache blocks that need to be coherent as non-cacheable until all CPUs enable their MMU and thus allows gem5 to boot MP systems with caches enabled (a requirement for booting an O3 cpu and thus an O3 CPU regression).
Diffstat (limited to 'src/arch/arm/tlb.cc')
-rw-r--r--src/arch/arm/tlb.cc10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc
index c59498212..942f85120 100644
--- a/src/arch/arm/tlb.cc
+++ b/src/arch/arm/tlb.cc
@@ -61,6 +61,7 @@
#include "sim/process.hh"
#if FULL_SYSTEM
+#include "arch/arm/system.hh"
#include "arch/arm/table_walker.hh"
#endif
@@ -72,7 +73,7 @@ TLB::TLB(const Params *p)
#if FULL_SYSTEM
, tableWalker(p->walker)
#endif
- , rangeMRU(1), miscRegValid(false)
+ , rangeMRU(1), bootUncacheability(false), miscRegValid(false)
{
table = new TlbEntry[size];
memset(table, 0, sizeof(TlbEntry) * size);
@@ -575,6 +576,11 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
}
}
+
+ if (!bootUncacheability &&
+ ((ArmSystem*)tc->getSystemPtr())->adderBootUncacheable(vaddr))
+ req->setFlags(Request::UNCACHEABLE);
+
switch ( (dacr >> (te->domain * 2)) & 0x3) {
case 0:
domainFaults++;
@@ -704,7 +710,7 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
#else
fault = translateSe(req, tc, mode, translation, delay, true);
#endif
- DPRINTF(TLB, "Translation returning delay=%d fault=%d\n", delay, fault !=
+ DPRINTF(TLBVerbose, "Translation returning delay=%d fault=%d\n", delay, fault !=
NoFault);
if (!delay)
translation->finish(fault, req, tc, mode);