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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:14 -0500 |
| commit | 527b735cfc1e9031dc0a63ab43b1eb2ecf1fa4ec (patch) | |
| tree | 61134ba71b8da4a6f288abcda2eb8517a1648891 /src/arch/arm/tlb.cc | |
| parent | 4491170df6e7a130c43d38d4220e5dff3c1dd214 (diff) | |
| download | gem5-527b735cfc1e9031dc0a63ab43b1eb2ecf1fa4ec.tar.xz | |
ARM: Implement and update the DFSR and IFSR registers on faults.
Diffstat (limited to 'src/arch/arm/tlb.cc')
| -rw-r--r-- | src/arch/arm/tlb.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 8e1baf126..f9257a005 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -299,7 +299,8 @@ TLB::translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode) if (sctlr.a || (flags & AllowUnaligned) == 0) { if ((vaddr & flags & AlignmentMask) != 0) { - return new DataAbort; + return new DataAbort(vaddr, (mode == Write), 0, + ArmFault::AlignmentFault); } } } |