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author | Dam Sunwoo <dam.sunwoo@arm.com> | 2010-06-02 12:58:18 -0500 |
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committer | Dam Sunwoo <dam.sunwoo@arm.com> | 2010-06-02 12:58:18 -0500 |
commit | 6c8dd32fa4f21771a2c83886b08c3d68be516044 (patch) | |
tree | 35a88b63e76ee57ffe73a1a2b118d2b2e676800c /src/arch/arm/tlb.cc | |
parent | 85ba2a32436aa7dde2319f213b5f410a80c6453a (diff) | |
download | gem5-6c8dd32fa4f21771a2c83886b08c3d68be516044.tar.xz |
ARM: Added support for Access Flag and some CP15 regs (V2PCWPR, V2PCWPW, V2PCWUR, V2PCWUW,...)
Diffstat (limited to 'src/arch/arm/tlb.cc')
-rw-r--r-- | src/arch/arm/tlb.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.cc b/src/arch/arm/tlb.cc index 05d65457c..7f02061b0 100644 --- a/src/arch/arm/tlb.cc +++ b/src/arch/arm/tlb.cc @@ -384,6 +384,16 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, if (nmrr.ir0 == 0 || nmrr.or0 == 0 || prrr.tr0 != 0x2) req->setFlags(Request::UNCACHEABLE); } + + // Set memory attributes + TlbEntry temp_te; + tableWalker->memAttrs(temp_te, 0, 1); + temp_te.shareable = true; + DPRINTF(TLBVerbose, "(No MMU) setting memory attributes: shareable:\ + %d, innerAttrs: %d, outerAttrs: %d\n", temp_te.shareable, + temp_te.innerAttrs, temp_te.outerAttrs); + setAttr(temp_te.attributes); + return trickBoxCheck(req, mode, 0, false); } @@ -409,6 +419,13 @@ TLB::translateFs(RequestPtr req, ThreadContext *tc, Mode mode, assert(te); } + // Set memory attributes + DPRINTF(TLBVerbose, + "Setting memory attributes: shareable: %d, innerAttrs: %d, \ + outerAttrs: %d\n", + te->shareable, te->innerAttrs, te->outerAttrs); + setAttr(te->attributes); + uint32_t dacr = tc->readMiscReg(MISCREG_DACR); switch ( (dacr >> (te->domain * 2)) & 0x3) { case 0: |