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author | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
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committer | Gene Wu <Gene.Wu@arm.com> | 2010-08-23 11:18:41 -0500 |
commit | d6736384b2bb280ec12d472cac6eb25a70b4af60 (patch) | |
tree | 4ab72a9724a1f349a6c9ddc3088e73d7cebd7f90 /src/arch/arm/tlb.hh | |
parent | 23626d99af9469b5a86f510e0542846f5af65cbd (diff) | |
download | gem5-d6736384b2bb280ec12d472cac6eb25a70b4af60.tar.xz |
MEM: Make CLREX a first class request operation and clear locks in caches when it in received
Diffstat (limited to 'src/arch/arm/tlb.hh')
-rw-r--r-- | src/arch/arm/tlb.hh | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index d1ba42b39..1bddd8497 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -78,8 +78,7 @@ class TLB : public BaseTLB // Because zero otherwise looks like a valid setting and may be used // accidentally, this bit must be non-zero to show it was used on // purpose. - MustBeOne = 0x20, - Clrex = 0x40 + MustBeOne = 0x20 }; protected: typedef std::multimap<Addr, int> PageTable; |