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author | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:03 +0100 |
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committer | Dylan Johnson <Dylan.Johnson@ARM.com> | 2016-08-02 10:38:03 +0100 |
commit | 4d5d47c173d3e649c7e620481d18ea93a3e09e79 (patch) | |
tree | 2a3663fcc250d5c24b1992a6d7b84c2fdf94a1ed /src/arch/arm/tlb.hh | |
parent | 89511856fe15077d4f568e3226aff66d1f3b39eb (diff) | |
download | gem5-4d5d47c173d3e649c7e620481d18ea93a3e09e79.tar.xz |
arm: Add TLBI instruction for stage 2 IPA's
This patch adds support for stage 2 TLBI instructions
such as TLBI IPAS2E1_Xt.
Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88
Diffstat (limited to 'src/arch/arm/tlb.hh')
-rw-r--r-- | src/arch/arm/tlb.hh | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index ef05bb421..f4530a219 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -275,6 +275,19 @@ class TLB : public BaseTLB */ void flushMva(Addr mva, bool secure_lookup, bool hyp, uint8_t target_el); + /** + * Invalidate all entries in the stage 2 TLB that match the given ipa + * and the current VMID + * @param ipa the address to invalidate + * @param secure_lookup if the operation affects the secure world + * @param hyp if the operation affects hyp mode + */ + void flushIpaVmid(Addr ipa, bool secure_lookup, bool hyp, uint8_t target_el); + + Fault trickBoxCheck(RequestPtr req, Mode mode, TlbEntry::DomainType domain); + Fault walkTrickBoxCheck(Addr pa, bool is_secure, Addr va, Addr sz, bool is_exec, + bool is_write, TlbEntry::DomainType domain, LookupLevel lookup_level); + void printTlb() const; void demapPage(Addr vaddr, uint64_t asn) override |