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author | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
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committer | Geoffrey Blake <geoffrey.blake@arm.com> | 2012-01-31 07:46:03 -0800 |
commit | af6aaf258171027af8d3cf0ef86dddff501a3ccb (patch) | |
tree | 3473845b7217b48dcf43460f0a90ca655a7018ed /src/arch/arm/tlb.hh | |
parent | ade53def9252a36a39b2c4bd61196355906f0505 (diff) | |
download | gem5-af6aaf258171027af8d3cf0ef86dddff501a3ccb.tar.xz |
CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
Brings the CheckerCPU back to life to allow FS and SE checking of the
O3CPU. These changes have only been tested with the ARM ISA. Other
ISAs potentially require modification.
Diffstat (limited to 'src/arch/arm/tlb.hh')
-rw-r--r-- | src/arch/arm/tlb.hh | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 3464e42b3..bdfa2fc9f 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -182,6 +182,12 @@ class TLB : public BaseTLB */ bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr); + /** + * Do a functional lookup on the TLB (for checker cpu) that + * behaves like a normal lookup without modifying any page table state. + */ + Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode); + /** Accessor functions for memory attributes for last accessed TLB entry */ void @@ -197,7 +203,8 @@ class TLB : public BaseTLB #if FULL_SYSTEM Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode, - Translation *translation, bool &delay, bool timing); + Translation *translation, bool &delay, + bool timing, bool functional = false); #else Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing); |