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| author | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:30 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2015-05-05 03:22:30 -0400 |
| commit | 23b9792681d4cd794b0ad74138160a37b8bdac8f (patch) | |
| tree | dd849032f615ec6a5ff43a6a2e93393d8f6fd5f7 /src/arch/arm/tlb.hh | |
| parent | 36f29496a019af4483430f17c4a6028b8dcfb2cf (diff) | |
| download | gem5-23b9792681d4cd794b0ad74138160a37b8bdac8f.tar.xz | |
arm: Remove unnecessary boot uncachability
With the recent patches addressing how we deal with uncacheable
accesses there is no longer need for the work arounds put in place to
enforce certain sections of memory to be uncacheable during boot.
Diffstat (limited to 'src/arch/arm/tlb.hh')
| -rw-r--r-- | src/arch/arm/tlb.hh | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index f3e3923da..6ed89af7c 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -136,8 +136,6 @@ class TLB : public BaseTLB int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU - bool bootUncacheability; - public: TLB(const ArmTLBParams *p); TLB(const Params *p, int _size, TableWalker *_walker); @@ -233,7 +231,6 @@ class TLB : public BaseTLB void printTlb() const; - void allCpusCaching() { bootUncacheability = true; } void demapPage(Addr vaddr, uint64_t asn) { // needed for x86 only |