arm: Share a port for the two table walker objects

This patch changes how the MMU and table walkers are created such that
a single port is used to connect the MMU and the TLBs to the memory
system. Previously two ports were needed as there are two table walker
objects (stage one and stage two), and they both had a port. Now the
port itself is moved to the Stage2MMU, and each TableWalker is simply
using the port from the parent.

By using the same port we also remove the need for having an
additional crossbar joining the two ports before the walker cache or
the L2. This simplifies the creation of the CPU cache topology in
BaseCPU.py considerably. Moreover, for naming and symmetry reasons,
the TLB walker port is connected through the stage-one table walker
thus making the naming identical to x86. Along the same line, we use
the stage-one table walker to generate the master id that is used by
all TLB-related requests.

1 files changed, 3 insertions, 10 deletions

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index 0be569fec..f3e3923da 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -163,7 +163,9 @@ class TLB : public BaseTLB
     /// setup all the back pointers
     virtual void init();
 
-    void setMMU(Stage2MMU *m);
+    TableWalker *getTableWalker() { return tableWalker; }
+
+    void setMMU(Stage2MMU *m, MasterID master_id);
 
     int getsize() const { return size; }
 
@@ -308,15 +310,6 @@ class TLB : public BaseTLB
      */
     virtual BaseMasterPort* getMasterPort();
 
-    /**
-     * Allow the MMU (overseeing both stage 1 and stage 2 TLBs) to
-     * access the table walker port of this TLB so that it can
-     * orchestrate staged translations.
-     *
-     * @return The table walker DMA port
-     */
-    DmaPort& getWalkerPort();
-
     // Caching misc register values here.
     // Writing to misc registers needs to invalidate them.
     // translateFunctional/translateSe/translateFs checks if they are