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| author | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:35 -0400 |
|---|---|---|
| committer | Andreas Hansson <andreas.hansson@arm.com> | 2012-10-15 08:12:35 -0400 |
| commit | 2a740aa09682c32eb8f1f8880f279c943d8c6ee1 (patch) | |
| tree | 61ca1dcb9336bc1f4dbc791c876875c1c260ca8d /src/arch/arm/tlb.hh | |
| parent | 9baa35ba802f2cfb9fb9ecdebf111f4cd793a428 (diff) | |
| download | gem5-2a740aa09682c32eb8f1f8880f279c943d8c6ee1.tar.xz | |
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.
The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
Diffstat (limited to 'src/arch/arm/tlb.hh')
| -rw-r--r-- | src/arch/arm/tlb.hh | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index a20957f6a..968699764 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -224,7 +224,7 @@ class TLB : public BaseTLB * * @return A pointer to the walker master port */ - virtual MasterPort* getMasterPort(); + virtual BaseMasterPort* getMasterPort(); // Caching misc register values here. // Writing to misc registers needs to invalidate them. |