diff options
| author | Nathanael Premillieu <Nathanael.Premillieu@arm.com> | 2015-05-26 03:21:42 -0400 |
|---|---|---|
| committer | Nathanael Premillieu <Nathanael.Premillieu@arm.com> | 2015-05-26 03:21:42 -0400 |
| commit | 31fd18ab156f86ec2fced0641d2c76fba60a7d2d (patch) | |
| tree | 7f02bc701f3b3a85c702ebe1d0546e15ca42a17c /src/arch/arm/tlb.hh | |
| parent | 53a360985b5d298e03ed0102d750b2c362ec1d90 (diff) | |
| download | gem5-31fd18ab156f86ec2fced0641d2c76fba60a7d2d.tar.xz | |
arm: Make address translation faster with better caching
This patch adds better caching of the sys regs for AArch64, thus
avoiding unnecessary calls to tc->readMiscReg(MISCREG_CPSR) in the
non-faulting case.
Diffstat (limited to 'src/arch/arm/tlb.hh')
| -rw-r--r-- | src/arch/arm/tlb.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 6ed89af7c..fba5775aa 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -312,6 +312,7 @@ class TLB : public BaseTLB // translateFunctional/translateSe/translateFs checks if they are // invalid and call updateMiscReg if necessary. protected: + CPSR cpsr; bool aarch64; ExceptionLevel aarch64EL; SCTLR sctlr; |