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| author | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-10-16 05:49:41 -0400 |
|---|---|---|
| committer | Andreas Sandberg <Andreas.Sandberg@ARM.com> | 2014-10-16 05:49:41 -0400 |
| commit | 9d35d48e848914fd6cf18b016cb9125c50e422c0 (patch) | |
| tree | 3216b47b402751d809c75c9c9cbaedeef0787597 /src/arch/arm/tlb.hh | |
| parent | 76b0ff9ecd8bd4818dff8a3cc811bee547b643b4 (diff) | |
| download | gem5-9d35d48e848914fd6cf18b016cb9125c50e422c0.tar.xz | |
arm: Add TLB PMU probes
This changeset adds probe points that can be used to implement PMU
counters for TLB stats. The following probes are supported:
* ArmISA::TLB::ppRefills / TLB Refills (TLB insertions)
Diffstat (limited to 'src/arch/arm/tlb.hh')
| -rw-r--r-- | src/arch/arm/tlb.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index b9025fa5f..06a51e5da 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -53,6 +53,7 @@ #include "mem/request.hh" #include "params/ArmTLB.hh" #include "sim/fault_fwd.hh" +#include "sim/probe/pmu.hh" #include "sim/tlb.hh" class ThreadContext; @@ -131,6 +132,9 @@ class TLB : public BaseTLB Stats::Formula misses; Stats::Formula accesses; + /** PMU probe for TLB refills */ + ProbePoints::PMUUPtr ppRefills; + int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU bool bootUncacheability; @@ -291,6 +295,8 @@ class TLB : public BaseTLB void regStats(); + void regProbePoints() M5_ATTR_OVERRIDE; + /** * Get the table walker master port. This is used for migrating * port connections during a CPU takeOverFrom() call. For |