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| author | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
|---|---|---|
| committer | Mitch Hayenga <mitch.hayenga@arm.com> | 2015-09-30 11:14:19 -0500 |
| commit | ccf4f6c3d7616c546d78eb21d22ebda812b5e2bb (patch) | |
| tree | 08581c6baa40737335733f39d4bab87611ddccee /src/arch/arm/tlb.hh | |
| parent | 9e07a7504c94973e7837d1d3e96dbdb8d95cfad3 (diff) | |
| download | gem5-ccf4f6c3d7616c546d78eb21d22ebda812b5e2bb.tar.xz | |
arm: Change TLB Software Caching
In ARM, certain variables are only updated when a necessary change is
detected. Having 2 SMT threads share a TLB resulted in these not being
updated as required. This patch adds a thread context identifer to
assist in the invalidation of these variables.
Diffstat (limited to 'src/arch/arm/tlb.hh')
| -rw-r--r-- | src/arch/arm/tlb.hh | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh index 63707dba2..35049db48 100644 --- a/src/arch/arm/tlb.hh +++ b/src/arch/arm/tlb.hh @@ -327,6 +327,7 @@ protected: HCR hcr; uint32_t dacr; bool miscRegValid; + ContextID miscRegContext; ArmTranslationType curTranType; // Cached copies of system-level properties |