MEM: Introduce the master/slave port sub-classes in C++

This patch introduces the notion of a master and slave port in the C++
code, thus bringing the previous classification from the Python
classes into the corresponding simulation objects and memory objects.

The patch enables us to classify behaviours into the two bins and add
assumptions and enfore compliance, also simplifying the two
interfaces. As a starting point, isSnooping is confined to a master
port, and getAddrRanges to slave ports. More of these specilisations
are to come in later patches.

The getPort function is not getMasterPort and getSlavePort, and
returns a port reference rather than a pointer as NULL would never be
a valid return value. The default implementation of these two
functions is placed in MemObject, and calls fatal.

The one drawback with this specific patch is that it requires some
code duplication, e.g. QueuedPort becomes QueuedMasterPort and
QueuedSlavePort, and BusPort becomes BusMasterPort and BusSlavePort
(avoiding multiple inheritance). With the later introduction of the
port interfaces, moving the functionality outside the port itself, a
lot of the duplicated code will disappear again.

1 files changed, 11 insertions, 2 deletions

diff --git a/src/arch/arm/tlb.hh b/src/arch/arm/tlb.hh
index daf59f01d..a20957f6a 100644
--- a/src/arch/arm/tlb.hh
+++ b/src/arch/arm/tlb.hh
@@ -214,8 +214,17 @@ class TLB : public BaseTLB
 
     void regStats();
 
-    // Get the port from the table walker and return it
-    virtual Port *getPort();
+    /**
+     * Get the table walker master port. This is used for migrating
+     * port connections during a CPU takeOverFrom() call. For
+     * architectures that do not have a table walker, NULL is
+     * returned, hence the use of a pointer rather than a
+     * reference. For ARM this method will always return a valid port
+     * pointer.
+     *
+     * @return A pointer to the walker master port
+     */
+    virtual MasterPort* getMasterPort();
 
     // Caching misc register values here.
     // Writing to misc registers needs to invalidate them.