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| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-02-19 09:51:31 +0000 |
|---|---|---|
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | 2019-05-23 08:32:25 +0000 |
| commit | e9c7c8168081e38d272e7c83e7f9503b7e8f162f (patch) | |
| tree | 4f568ee35bfe6f0b28d6418b123df48a1174f127 /src/arch/arm/tlb.hh | |
| parent | 92518ec8437b422f86f7c315a83d9c2aa5fdbe1b (diff) | |
| download | gem5-e9c7c8168081e38d272e7c83e7f9503b7e8f162f.tar.xz | |
arch-arm: Expose haveGicv3CPUInterface to the ISA interface
Change-Id: I36232b7618ad875983f34b741c51f12ddb9ae166
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17989
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Diffstat (limited to 'src/arch/arm/tlb.hh')
0 files changed, 0 insertions, 0 deletions