diff options
| author | Gabe Black <gabeblack@google.com> | 2018-11-19 18:14:16 -0800 |
|---|---|---|
| committer | Gabe Black <gabeblack@google.com> | 2019-01-31 11:02:05 +0000 |
| commit | 5edfb67041ad1c246f4ceca147f06b9db3c0ecc3 (patch) | |
| tree | 22cc08624db8bfa11e4ea7c9817a864ebc2ea706 /src/arch/arm/tracers | |
| parent | 25474167e5b247d1b91fbf802c5b396a63ae705e (diff) | |
| download | gem5-5edfb67041ad1c246f4ceca147f06b9db3c0ecc3.tar.xz | |
arch: cpu: Rename *FloatRegBits* to *FloatReg*.
Now that there's no plain FloatReg, there's no reason to distinguish
FloatRegBits with a special suffix since it's the only way to read or
write FP registers.
Change-Id: I3a60168c1d4302aed55223ea8e37b421f21efded
Reviewed-on: https://gem5-review.googlesource.com/c/14460
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Diffstat (limited to 'src/arch/arm/tracers')
| -rw-r--r-- | src/arch/arm/tracers/tarmac_parser.cc | 28 | ||||
| -rw-r--r-- | src/arch/arm/tracers/tarmac_record.cc | 2 |
2 files changed, 15 insertions, 15 deletions
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc index 67bbb1493..860bb1b0b 100644 --- a/src/arch/arm/tracers/tarmac_parser.cc +++ b/src/arch/arm/tracers/tarmac_parser.cc @@ -647,35 +647,35 @@ TarmacParserRecord::TarmacParserRecordEvent::process() break; case REG_S: if (instRecord.isetstate == ISET_A64) - value_lo = thread->readFloatRegBits(it->index * 4); + value_lo = thread->readFloatReg(it->index * 4); else - value_lo = thread->readFloatRegBits(it->index); + value_lo = thread->readFloatReg(it->index); break; case REG_D: if (instRecord.isetstate == ISET_A64) - value_lo = thread->readFloatRegBits(it->index * 4) | - (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << + value_lo = thread->readFloatReg(it->index * 4) | + (uint64_t) thread->readFloatReg(it->index * 4 + 1) << 32; else - value_lo = thread->readFloatRegBits(it->index * 2) | - (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << + value_lo = thread->readFloatReg(it->index * 2) | + (uint64_t) thread->readFloatReg(it->index * 2 + 1) << 32; break; case REG_Q: check_value_hi = true; if (instRecord.isetstate == ISET_A64) { - value_lo = thread->readFloatRegBits(it->index * 4) | - (uint64_t) thread->readFloatRegBits(it->index * 4 + 1) << + value_lo = thread->readFloatReg(it->index * 4) | + (uint64_t) thread->readFloatReg(it->index * 4 + 1) << 32; - value_hi = thread->readFloatRegBits(it->index * 4 + 2) | - (uint64_t) thread->readFloatRegBits(it->index * 4 + 3) << + value_hi = thread->readFloatReg(it->index * 4 + 2) | + (uint64_t) thread->readFloatReg(it->index * 4 + 3) << 32; } else { - value_lo = thread->readFloatRegBits(it->index * 2) | - (uint64_t) thread->readFloatRegBits(it->index * 2 + 1) << + value_lo = thread->readFloatReg(it->index * 2) | + (uint64_t) thread->readFloatReg(it->index * 2 + 1) << 32; - value_hi = thread->readFloatRegBits(it->index * 2 + 2) | - (uint64_t) thread->readFloatRegBits(it->index * 2 + 3) << + value_hi = thread->readFloatReg(it->index * 2 + 2) | + (uint64_t) thread->readFloatReg(it->index * 2 + 3) << 32; } break; diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc index 5dbb847e5..51fbf2c0a 100644 --- a/src/arch/arm/tracers/tarmac_record.cc +++ b/src/arch/arm/tracers/tarmac_record.cc @@ -235,7 +235,7 @@ TarmacTracerRecord::TraceRegEntry::updateFloat( regValid = true; regName = "f" + std::to_string(regRelIdx); - valueLo = bitsToFloat32(thread->readFloatRegBits(regRelIdx)); + valueLo = bitsToFloat32(thread->readFloatReg(regRelIdx)); } void |