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| author | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
|---|---|---|
| committer | Gabe Black <gblack@eecs.umich.edu> | 2010-06-02 12:58:16 -0500 |
| commit | 05bd3eb4ec3d9fea3dbc46112a47459085d3011c (patch) | |
| tree | 58d50fab58de1e9165bfc28986913811b26b9568 /src/arch/arm/types.hh | |
| parent | b93ceef5381b7c84b6887b5299ae81ff48ef45c9 (diff) | |
| download | gem5-05bd3eb4ec3d9fea3dbc46112a47459085d3011c.tar.xz | |
ARM: Implement support for the IT instruction and the ITSTATE bits of CPSR.
Diffstat (limited to 'src/arch/arm/types.hh')
| -rw-r--r-- | src/arch/arm/types.hh | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh index 95e5a18a0..dd6b7e610 100644 --- a/src/arch/arm/types.hh +++ b/src/arch/arm/types.hh @@ -51,6 +51,12 @@ namespace ArmISA typedef uint32_t MachInst; BitUnion64(ExtMachInst) + Bitfield<63, 56> newItstate; + // ITSTATE bits + Bitfield<55, 48> itstate; + Bitfield<55, 52> itstateCond; + Bitfield<51, 48> itstateMask; + // FPSCR fields Bitfield<41, 40> fpscrStride; Bitfield<39, 37> fpscrLen; |